1. Field of the Invention:
The present invention relates to a semiconductor memory device capable of writing data to memory cells, such as a static random access memory (SRAM) and a dynamic random access memory (DRAM).
2. Description of the Related Art:
As shown in FIG. 5, in a semiconductor memory device capable of writing data to memory cells, such as an SRAM and a DRAM, write data is input from a data input pad 21 connected to a data input buffer 22. In this semiconductor memory device, the data input buffer 22 is constituted by an inverter circuit. In a logic gate such as an inverter circuit, an input threshold level has a noise margin with respect to an output level. Therefore, when data at an H level or an L level is input, the input data can be output at an L level or an H level, respectively (even though these H level and L level are close to each other to some extent). Thus, the data input buffer 22 is used for restoring the input data, which was deteriorated while being transmitted through a bus line or the like, to output data at an H level or an L level.
The restored input data which is set to the appropriate output level by the data input buffer 22 is transmitted through a single data line 23 to a group of memory cells 24. The data line 23 is provided on a semiconductor chip over a long length, so that the data is also deteriorated while being transmitted through the data line 23. In order to overcome this problem, associated with the group of memory cells 24, a logic gate 25 (shown as an inverter circuit in the figure) is connected to an end of the data line 23, whereby the data deteriorated while being transmitted through the data line 23 is restored to an H level or an L level again. The output data from the logic gate 25 is also inverted by an inverter circuit 26 and the outputs of logic gates 25 and 26 are transmitted to a column transfer gate 27.
The column transfer gate 27 operates as follows:
A pair of bit lines 28 are selected from a number of pair of bit lines in a memory cell array by a column decoder (not shown). One bit line B of the selected pair of bit lines 28 is connected to the output of the logic gate 25, and the other bit line B of the selected pair of bit lines 28 is connected to the output of the inverter circuit 26. On the basis of data on the data line 23, data at an H level and an L level which have a complementary relationship with each other are produced through the logic gate 25 and the inverter circuit 26 and transmitted to the bit lines 28. The transmitted data is written in a memory cell 29 selected by a row decoder (not shown).
In recent years, with each advance to the next IC memory generation, a great increase in memory capacity in a semiconductor memory device is realized by decreasing the area of a memory cell as well as increasing the area of a chip. Thus, the length of the data line 23 extending from the data input buffer 22 to the array of memory cells 24 in FIG. 5 is much more increased along with the increase in the area of the chip, resulting in an increase in distributed capacitance of the data line 23.
Because of this increase in distributed capacitance, in a conventional semiconductor memory device, the signal transition time is remarkably delayed along with the increase in the distributed capacitance of the data line 23, causing a further problem of decreasing access speed.
Some semiconductor memory devices in recent years have the data line 23 with a length of about 20 mm. Suppose, for example, that the distributed capacitance per unit length of the data line 23 is 0.5 pF/mm, the distributed capacitance for full length becomes 10 pF (=20 mm.times.0.5 pF/mm). In this example, voltage V, capacitance C, and charge Q have the following relationship: ##EQU1## The charge Q, an instantaneous current i, and time t have the following relationship: EQU Q=.intg.idt (II)
If the charge Q is eliminated from Equations I and II, the following relationship is obtained. ##EQU2## Moreover, suppose that the instantaneous current i is a constant current I, so that the integration term in Equation III can be represented by the product of the current I and the time t. Thus, the following relationship can be obtained. ##EQU3## Thus, if the data line 23 is charged by using a transistor with a driving capacity of 3 mA until the voltage level thereof is increased from a GND level to 70% of a V.sub.cc level, where V.sub.cc is 5 V: ##EQU4## As shown in Equation V, it takes about 11.7 nano sec. to charge the data line 23 in a conventional device.
Because of this, in the case of the semiconductor device shown in FIG. 5, as shown in FIG. 6, for example, at time t.sub.11, input data S.sub.21 of the data input pad 21 is switched from an H level to an L level. When the data input buffer 22 outputs an H level, an electrical potential S.sub.22 at the end of the data line 23 is gradually increased from the GND level to the V.sub.cc level. At t.sub.12 which is 11.7 nano sec. ahead of t.sub.11, when the electrical potential S.sub.22 reaches 70% of the V.sub.cc level, an output S.sub.23 of the logic gate 25 is gradually switched to an L level and an output S.sub.24 of the inverter circuit 26 is switched to an H level. Then the bit lines B and B of the pair of bit lines 28 are discharged and charged via the column transfer gate 27.
As a result, in a conventional semiconductor memory device, it is necessary that the electrical potential S.sub.22 at the end of the data line 23 is increased up to the V.sub.cc level and decreased to the GND level (i.e., the electrical potential S.sub.22 should fully swing between the V.sub.cc level and the GND level). There further arises the problem in that access speed is decreased due to the delay of the charging and discharging time caused by the distributed capacitance of the data line.